STAR3000

Description

STAR3000 is designed to digitize a differential analog signal, with an SNR of >96dB over a signal bandwidth of 10Hz, with a nominal sampling rate of 32.768kHz. The ADC is designed in a 0.18µm CMOS Silterra process and designed to run off a 1.8V (±10%) supply, where the ADC consumes 30uA of current. The ADC uses an enhanced input stage to allows the ADC to sample voltages as low as -0.25V. A second-order architecture Delta-Sigma architecture is used to achieve an SQNR of > 100dB over a 10Hz bandwidth. Chopping is used in all key opamps to minimize 1/f noise in the ADC output.

Features

• Programmable input range

• Enhanced input stage enables ADC to quantize inputs between -0.25 and +0.25V

• Low 1/f noise enabled by using chopped opamps in key parts of circuit

• Good linearity as ADC uses a 1-bit quantizer

• Low current consumption (30uA)

• 16-bit thermal noise-floor over 10Hz input bandwidth

• Test-bus access to internal key internal nodes

• Digitally enhanced ADC stability

• Optional digital CIC filter available

• Optional I2C/SPI digital interface available

• Optional within 1% factory calibrated internal 32.768kHz oscillator available

• Optional LDO to generate 1.8V from 3.3V

• -40°C to 85°C operating range

• 0.18um CMOS Silterra Process

• Designed to operate at 1.8V ±10%

• Macro area: 580um x 450um

• .GDS ready

• Silicon verified

Applications

• Battery meter/Gas gauge

• Sensor applications

• Power applications

• Base-band digitization for DC type signals with slowly varying bandwidth

• On-chip test-bus digitization